IBM and Siemens develop design tools for IBM's 3D nanostack

The October 14th research collaboration pairs IBM's device work with Siemens EDA tools as IBM prepares an early nanostack design kit for 2027.

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Primary source: IBM Newsroom

Why it matters

IBM is pairing transistor research with EDA work while nanostack is still being defined. The collaboration could help chip designers evaluate the architecture, but IBM has not established a manufacturing schedule or named a production partner.

IBM and Siemens model the design challenges of 3D nanostack transistors — The October 14th research collaboration pairs IBM's device work with Siemens EDA tools as IBM prepares an early nanostack design kit for 2027.

IBM and Siemens announced a research collaboration on October 14th to develop the design, simulation and lithography methods IBM says it needs to move its 7-angstrom nanostack transistor architecture toward manufacturing. Engineers need tools to design and test a new device structure before it can become a chipmaking process. The companies' announcement describes the work as research.…

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